os: x86 cpuid natives and pure decoders (OS slice 3, step 2a) #538
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Goal
Step 2a of #127 (OS slice 3): the
x86/module ofstd/oswith its two natives and the pure decoders, plus the public typesdescribewill return.Processor.describeitself and the per-system halves (Windows topology, Linux/macOS counts and caches, Arm64 features from the system) are not in this issue: they are step 2b, filed when this one lands.Why the cut: step 2 as written in #127 spans
runtime/os/x86.c, the decoders, three per-system halves and the Arm64 feature sources. That is more than one PR of one or two commits, so only the first sub-step is filed (per the definition of ready).Design record
docs/design/OS.mdsection 7 ("x86 —runtime/os/x86.c,native type X86, on.X64"), section 5.2 (ProcessorDescription,ProcessorCache,ProcessorFeature), the feature-list paragraph after 5.2, slice 3 of section 10.Scope
runtime/os/x86.c:X86.cpuid(leaf, subleaf, var eax, var ebx, var ecx, var edx)andX86.extendedControlRegister(var low, var high): Bool(xgetbv(0), false whereOSXSAVEis not set), guarded for.X64like the other per-system files, no#ifdefinside a function.std/os/src/x86/native.trb(native type X86) andstd/os/src/x86/processor.trb: pure decoders over register integers: vendor (leaf 0), brand string (leaves0x80000002to0x80000004), feature bits (leaves 1 and 7, plusxgetbvfor AVX/AVX-512 usability), caches (leaf 4, or0x8000001Don AMD), and topology (packages, cores, logical processors from leaves 1, 4,0xB/0x1F,0x80000008).ProcessorCacheandProcessorFeatureas in OS.md 5.2 (the list stays closed; Arm64 cases are declared now, filled in step 2b),ProcessorDescriptiononly if the decoders need it as the carrier; otherwise it comes with 2b.std/os/tests/x86.test.trb: tests that feed the decoders register values captured from real processors (at least one Intel and one AMD, one without AVX-512, one with; a hybrid-core Intel for leaf0x1A/0x1Fif capturable), runnable on every machine and architecture.docs/standard-library/os.mddocuments the new public types; theskills/copy is regenerated.Acceptance criteria
X86.cpuid(0, 0, ...)returns a vendor string that equals the decoder's output for the same registers; on other architectures the module is absent and the std still builds (no newUnsupportedleaks into public API).ProcessorFeature.Avx/Avx2/Fma/Avx512Foundationare reported only whenOSXSAVEand the matchingxgetbvbits say the OS saves the registers (tested with a register set where the CPU has the bit but the OS does not).torb format --checkclean on touched files;sh tools/gates.sh agreen in forge CI; docs check andskills/regeneration clean.Seed impact
None expected: new std names and one new native type; the compiler imports none of them by string. If CI shows a seed dependency, fall back to the two-commit rule (native and std first, consumer second); the seed refresh itself stays with the owner.
Size
One PR, two Conventional Commits:
feat(os): x86 cpuid and extendedControlRegister nativesandfeat(os): x86 decoders for vendor, brand, topology, caches and features(docs and tests ride with the second).Dependencies
Step 1 (#488) landed (
f12a2a4d). Part of #127; step 3 (frequencies) is not filed yet.[loop:torbscript] claim implement by session:loop-torbscript-20261028 until 2026-10-28T11:30Z
[loop:torbscript] release implement: worker lost its execution context before pushing anything (no branch exists). Respawning.
[loop:torbscript] claim implement (respawn) by session:loop-torbscript-20261028 until 2026-10-28T11:40Z
[loop:torbscript] release implement: PR #541 (
loop/538-os-x86-decoders, head81d388a) is open and mergeable. Commits: cpuid/extendedControlRegister natives, x86 decoders (vendor, brand, topology, caches, features), runtime README stamp, and a fix making the ProcessorCache/ProcessorFeature doc examples self-contained (addresses the tier A failure ond80c806, run 2044). CI run 2050 on81d388ais queued behind the single linux-x64 runner. Tier B is expected red (pre-existing on main, fixed by #536). The follow-up worker lost its execution context; remaining CI verdict goes to the merge gate. Claim released.[loop:torbscript] claim implement (fix: tier A red on PR #541) by session:loop-torbscript-20261028 until 2026-10-28T14:40Z
[loop:torbscript] release implement: the fix worker was killed after pushing head
b9aec30to PR #541 (tier A fix); CI on that head is pending behind the single linux-x64 runner. Nothing left to implement until CI settles. next: waiting (CI on PR #541 and merge gate)[loop:torbscript] claim implement (fix: PR #541 tier B and gates red on
b9aec30; #536 landed on main, rebase and re-read) by session:loop-torbscript-20261028 until 2026-10-28T17:35Z[loop:torbscript] review: tier B and gates on
b9aec30failed only on the four inherited resource conformance programs (resource-bytes/-name/-text budgets, resource-missing); 330 of 334 passed, none of this PR. #536 has landed on main (403ee176), so I rebased the five commits onto it (linear, no merge commits, check-commits clean) and force-pushed with lease to loop/538-os-x86-decoders, new headacf8510. No code change was needed. Forge CI run 2061 onacf8510: tier A, tier B, gates, bootstrap, same-C, playground, release-sync and pdisc all green. I dropped the WIP prefix from the PR title since it is ready. Worktree removed. next: waiting (merge gate review of PR #541). Worker tokens: not exposed to the worker; roughly 60k, most of it spent waiting on the CI queue.[loop:torbscript] close: PR #541 landed on main (
acf85102). Its tier A, tier B and gates were green on the PR head; the push CI of the landed commit is still pending. next: waiting (main CI onacf85102, then close with the commit link)[loop:torbscript] close: PR #541 landed on main as
acf8510(acf8510278); main CI on that commit is green (bootstrap, tier A, tier B, gates). Step 2a of #127 is done, the epic continues with its next step. Closing.